1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor memory device including a circuit for storing an operation state thereof.
2. Description of the Related Art
Semiconductor devices, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), have circuits used to set their operation states. The circuits may include a mode register set. The operation states of a semiconductor memory device may include Column Address Strobe (CAS) latency, burst type, a burst length, bank grouping mode, and DLL on/off. The mode register set may store data corresponding to the operation state in response to a signal inputted from an external controller. More specifically, the semiconductor memory device may enable a setting operation of the mode register set in response to an external command signal, and store desired data in the mode register set based on data inputted through an address pin. Then, the semiconductor memory device may set the operation state thereof based on the data stored in the mode register set.
Recently, semiconductor memory devices have developed to suit a variety of requests from users. This means that the operation states of semiconductor memory devices have diversified. The diversification of the operation states may indicate that more data and more varieties of data are stored in the mode register set. Thus, it is likely that the configurations and operations of circuits related to the mode register set may change in various ways.